Mehul Parmar

About Mehul Parmar

With over 12 years of experience in the semiconductor industry, I am a Product and Manufacturing Test Development Engineer at Google, where I design, develop, and execute hardware tests for various products and platforms. I have a Master of Science degree in Electrical and Electronics Engineering from California State University and a strong background in device characterization, signal integrity, and high speed IO.My core competencies include automatic test equipment (ATE), NAND and SOC products, and hardware test development. I have led and collaborated on multiple projects involving 3D NAND high speed IO characterization, burn test tape development, memory failure debug and fault isolation, SOC bring-up, pattern conversion, MBIST testing, and DFT methodologies. I have also worked extensively with tools such as Verigy 93K, oscilloscopes, and burn-in chambers. My mission is to deliver high-quality and reliable products that meet the expectations and needs of customers and stakeholders.

Experience

1. Product and Test Manufacturing Engineer

   Google

   Jul 2023 — Present · Sunnyvale, CA, US

   Spearheaded the development and implementation of pioneering HTOL test methodology for new SOC products, encompassing board design, vendor selection, cross-functional requirements definition, DOE development, and data analysis in collaboration with product engineers.Accelerated time-to-market during NPI by providing strategic oversight of pattern conversion and automation, collaborating with DFT and IT teams for timely and high-quality test solutions.Optimizing HVM test program release cycles by championing vendor collaboration, test procedure definition and documentation, leading NPI process checklists for seamless transitions for NPI to HVM ramp, and driving continuous improvement through proactive learnings analysis.Work with cross-functional teams and external partners to successfully execute New Product Introduction (NPI) builds for SOC, ensuring on-time and on-quality delivery. Driving all aspects of program management, including schedule, risk mitigation, factory readiness, and supply chain deliverables, while acting as the primary liaison between Google\'s Supply Chain and key stakeholders. Identified and implemented process improvements across internal and external workflows, resulting in increased efficiency and streamlined operations.

Education

• C. U. Shah College of Engineering and Technology

  Bachelor, Engineering; Electronics and Communication Engineering

  2005 — 2009

• California State University

  Masters of Science, Electrical and Electronics Engineering

  2010 — 2013

Skills

• Dft
• Mbist Debug
• Jtag
• Perl
• Verilog
• C
• Vhdl
• Integrated Circuit Design
• Modelsim
• Debugging
• Xilinx
• Cadence Virtuoso
• Systemverilog
• Vlsi
• Sata
• Linux
• Synopsys Tools
• Good Communication
• Team Leadership
• Quick Learner
• Tcl
• Asic
• Static Timing Analysis
• Vcs
• Caching
• Assembly
• Scripting
• Rtl Design
• Virtual
• Architecture
• Fpga
• Storage
• Rtl Coding
• Pcie
• Functional Verification
• Soc
• Physical Design
• Formal Verification
• Logic Design
• Fault Isolation