Meher Aditya Chakka
Senior Silicon Design Engineer @ AMD
- Role
- Senior Silicon Design Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Meher Aditya Chakka
ASIC Verification Engineer with a (6+) year working experience in the SOC involving High Resolution Image Sensors. Skilled in hardware verification methodology (UVM) and design languages such as: SystemVerilog, Verilog and Scripting languages - Perl, Python.
Experience
Senior Silicon Design Engineer
Jun 2024 — Present · Hyderabad, IN
Serdes dv team
Education
Vellore Institute of Technology (VIT)
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
2016 — 2020
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Micro electronics
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.