Mehak Manchanda
Memory Layout Engineer
- Role
- Lead Engineer at HCLTech
- Location
- New Delhi, IN
- LinkedIn followers
- 500 followers
About Mehak Manchanda
I have 3 years of work experience in VLSI design/semiconductor industry. Major role is in physical/ backend design which includes full custom layout, physical verification, memory compiler designs, validations, floorplanning. Good knowledge of memory designs, IC layout rules, bitcell, decoder, sense amp. Hands-on experience on Full chip memory mask layout & tapeout
Experience
Lead Engineer
May 2023 — Present · Noida, IN
Education
Guru Gobind Singh Indraprastha University
Bachelor of Technology, Electrical, Electronics and Communications Engineering
2015 — 2019
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