Mehak Malhotra

WORK HISTORY

EDUCATION

SKILLS

ABOUT MEHAK MALHOTRA

Approx 6 years of experience in Memory Layout design which comprises of leafcell Layout development as well as all other Backend activities appreciated in Digital Memory Design.• Have experience of working in memory layout development in FDSOI technology for 28 nm apart from CMOS bulk technologies of 180nm, 130nm, 55nm, 45nm, 32nm and 28 nm.• Experience in Floorplanning, Leaf cell development, Cut assembly and Compiler development.• Experience in Cut development of memory qualification vehicle. • Good knowledge of all layout constraints which include : Electromigration, Finfet stability, Self heating, Shielding, Antenna Effects, Latchup Effect, Well Proximity Effects, Analog Matching, Parasitic Matching, DFM Implementation, DRC,LVS,SRD,LFD, etc. • Good Analytical Skills prerequisite for the various verifications.• Hands on experience of many development and verification related tools.(Virtuoso, CDesigner, Calibre, Apache TOTEM, Star RC etc.)• Basic command over Cadence SKILL language• Responsible for providing technical trainings to the new joiners in team on layout domain and compiler development process flow.• Presented in EDA conferences in Noida and Bangalore.• Responsible for Quality review of Backend products and testchip deliveries• Energized by technically challenging situations. Having the self driven motivation and love to be a team player.• Believe in making ease-of-work and right-from-construct approach.• Experience in training new comers and technically grooming them.• Always ready to take initiative in co-curricular in my team or on site level like planning team outings, team building activities, celebrations, on site or off site apart from my busy schedule.