Meghana V
RTL Design Engineer
- Role
- Rtl Design Engineer at Micron Technology
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Meghana V
ASIC VLSI Design Engineer with 3+ years of experience in frontend and backend tools for RTL design and integration.Expertise in tools like Spyglass (Lint, CDC, DFT), verification compiler ( lint,CDC, low power),defacto, prime power, power artist,Fusion Compiler, Conformal LEC, and Caliber for design rule checks, synthesis using fusion compiler and SAGE ATPGHands-on experience with RTL integration and signoff, including using Magillem for IP integration and generating RTL designs.Proficient in Verilog and System Verilog, with experience in RTL coding, debugging.Skilled in analyzing violations.An quick learner with strong analytical and problem-solving abilities.Currently pursuing M.Tech for working professionals from BITS Pilani, aiming to further specialize in cutting-edge VLSI design technologies.
Experience
Rtl Design Engineer
Nov 2025 — Present · Bengaluru, IN
working from leadsoc
Education
RGUKT Basar
Pre University Course , Maths Physics Chemistry
Birla Institute of Technology and Science, Pilani
M.tech, Microelectronics
RGUKT Basar
B.tech , Electronics and Communication Engineering
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