Meet Patel
Sr Silicon Design Engineer @AMD
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WORK HISTORY
Sr Silicon Design Engineer @AMD
Markham, ON, CA
EDUCATION
The H B Kapadia New High School
HSC - 12 Grade
The H B Kapadia New High School
SSC - 10 Grade
University of Waterloo
Master of Engineering - MEng
NIRMA UNIVERSITY
Bachelor of Technology - BTech
ABOUT MEET PATEL
My Skills 1. RTL design using Verilog 2. Design For Test (DFT) knowledge 3. HDL with knowledge of ASIC design 4. Good understanding of Digital Electronics concepts. Proficient in C language Besides this, eager to learn new things and develop skills according to need. • Career Objective To build upon and enhance my professional skills in a reputed and dynamic organization that gives me the opportunity to evolve in a professional manner.
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