Meenakshi Devineni
VLSI & FPGA Engineer | RTL Design & Verification | ASIC & Physical Design | Cadence, Synopsys, Xilinx | ASU EE MS Grad | VLSI Internship @ L&T Tech | Open to Design & Verification Roles | Semiconductor Enthusiast
- Role
- Physical Design Engineer at L&T Technology Services
- Location
- Los Angeles, CA, US
- LinkedIn followers
- 500 followers
About Meenakshi Devineni
I\'m an Electrical Engineering grad from ASU with a soft spot for semiconductors, stubborn…
Experience
Physical Design Engineer
Jul 2024 — Present · US
Education
Arizona State University
Master's degree, Electrical Engineering
KL University
Bachelor of Technology - BTech, Electronics and Communications Engineering
2018 — 2022
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