Maruf Abir Bappy

About Maruf Abir Bappy

Industrially experienced in the full flow of OTP & SRAM memory, analog & mixed-signal IC layout design & verification from block level to top-level design and GDS generation, physical verification(DRC, LVS, DRC, EM, IR) and tape-out using commercial EDA tools. Standard Cell Library Design, Characterization, Logic Equivalence Check (LEC), Manufacturing Analysis and Scoring (MAS) check, and Power Performance Area (PPA) analysis.Low power, high-performance VLSI circuit design for AI and IoT application.Test Chip Layout design, physical verification, simulation, tape-out, and Si data correlation.

Experience

1. Ic Mask Design

   Ulkasemi

   Aug 2016 — Present · Dhaka, BD

   Developed a full Standard Cell Library for different technology nodes using Cadence Virtuoso, Cadence Liberate, Cadence Conformal LEC, Cadence Voltus.Designed 6 port SRAM, OTP memory layout and completed full flow of physical verifications (LVS, DRC, ERC, MAS).Designed multiple analog (VSWITCH, Level Shifter, Current Mirror) block layout and verify the physical verificationDesigned GPIO and Bandgap layout and verify the physical verificationDesigned and taped-out multiple test chips for different nodes’ PDKs in Cadence Virtuoso, Star-RC, Hspice.Designed 16-bit 6T SRAM, DLL using GF 12LP PDK.Basic Analog Circuit Design (2 Stage Amplifier, ADC, DAC)Worked on CMOS device modeling using BSIM software

Education

• American International University-Bangladesh

  B.Sc

  2010 — 2013

Skills

• Electronics
• Matlab
• Fpga
• C++
• Xilinx
• Autocad
• Microsoft Excel
• Powerpoint
• C
• Verilog
• Pspice
• Microsoft Office
• Electrical Engineering
• Microcontrollers
• Vhdl
• Pcb Design
• Labview
• Digital Electronics
• Teamwork
• Digital Signal Processors
• Power Electronics