J Tazeer
Sr Silicon Design Engineer at AMD
- Role
- Sr Silicon Design Engineer at AMD
- Location
- Kurnool, AP, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About J Tazeer
Skilled in Universal Verification Methodology (UVM),SystemVerilog, and Application-Specific Integrated Circuits (ASIC). Strong quality assurance professional with a Bachelor of Technology focused in Ece from G. Reddy Engineering College,(Autonomous), Kurnool.
Experience
Sr Silicon Design Engineer
Dec 2023 — Present · Hyderabad, IN
Education
G. Pullla Reddy Engineering College, (Autonomous), Kurnool
Bachelor of Technology, Ece
2014 — 2018
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