Faizan Khan

About Faizan Khan

RTL Design Engineer with 4+ years of experience in RTL design, FPGA prototyping, and high-speed digital system development. Experienced in developing physical layer RTL for PCIe Gen5/Gen6 and CXL 2.0/3.0 protocols. Proficient in VHDL, SystemVerilog, and Verilog, with strong expertise in timing closure, CDC analysis, and board-level debugging on Xilinx FPGA platforms. Proven track record of delivering complex FPGA-based RTL designs with optimized performance and efficient resource utilization.

Experience

1. Lead Engineer

   Logic Fruit Technologies

   Apr 2025 — Present · Gurugram, IN

   Leading FPGA design activities for high-speed interface and SoC prototyping projects• Driving RTL architecture, integration, and validation for PCIe Gen6 and CXL 2.0/3.0• Overseeing timing closure, CDC analysis, and board-level debugging on Xilinx FPGA platforms• Coordinating with cross-functional teams for system integration and project delivery• Mentoring junior engineers and reviewing RTL design and implementation

Education

• Birla Institute of Technology, Mesra

  Bachelor of Technology - BTech, Electronics and Communications Engineering

• Delhi Public Convent School Baheri Ballia

  Secondary School Examination, Science

• Maven Silicon

  Intern, VLSI

• Oxford Public School Gorakhpur

  Senior School Certificate Examination, Science