Ahsanul Abeed

About Ahsanul Abeed

Semiconductor Yield & Product Development Engineer with 6+ years of experience advancing…

Experience

1. Failure and Yield Analysis R & d Engineer

   Intel

   Feb 2022 — Present · Hillsboro, OR, US

   Drive research and development work on silicon debug and characterization for Intel’s current and next-generation chips, identifying yield limiters and improving detection models for layout sensitive defects to support NPI and ramp readiness. Isolate chip/die level defect using electrical testing, V/f shmoo and optical emission techniques, enhance test coverage by developing and debugging test pattern/vector and scripting for tester development and ATE flows. Lead DOE-style analysis and EFA/PFA investigations by performing layout and schematic analysis and circuit-level debug in Cadence Virtuoso, Avalon, and ICV to identify design, process, and yield issues. Develop and productize Defect Analysis Tools to analyze data from class burn-in to final failure mode detection, integrating electrical fault isolation, nanoprobing, physical failure analysis, and TEM/EDX analysis to predict defect models and specifications based on Python scripting, SQL database interaction and Power BI dashboard visualization. Develop training materials and conduct training sessions for current and new team members across the organization.

Skills

• Semiconductor Device
• Cyber Security
• Verilog
• Pspice
• Computer Architecture
• Vhdl
• Quartus
• Analog Circuit Design
• Electrical Engineering
• Research
• Microcontrollers
• Vlsi
• Digital Logic Design
• Power Electronics
• Matlab