Mazek Kukkady

About Mazek Kukkady

Principal Design Engineer at Cadence Design Systems- Electrical Engineering Masters Graduate from USC (4.0 GPA)- Course Mentor for Computer System Organization course at USC- Course Grader for MOS VLSI Circuit Design and Computer System Architecture courses at USC-Skills- Hardware Description Languages: Verilog and VHDL- Scripting: Perl- Simulation: Modelsim, NCSim (ASIC)- Synthesis: Xilinx ISE (FPGA), Synopsys DC (ASIC)- Place and Route: Cadence Encounter (ASIC)- Debugging: Chipscope- EDA tools: Cadence Virtuoso, Cadence Spectre - Experience with Cadence EDA tools like Cadence Virtuoso and Cadence Spectre- Programming languages: C/C++- Also worked on 802.11a/b/g/n embedded systems at Ittiam-

Experience

1. Senior Principal Design Engineer

   Cadence

   Jan 2020 — Present · San Jose, CA, US

Education

• RVCE

  BE, Electronics and Communication

  2006 — 2010

• University of Southern California

  Master's degree, Electrical and Electronics Engineering

  2012 — 2014

Skills

• Cadence Spectre
• Perl
• Embedded Systems
• Modelsim
• Perl Script
• Logic Design
• Field-Programmable Gate Arrays (Fpga)
• C
• Debugging
• Rtl Design
• Very-Large-Scale Integration (Vlsi)
• Static Timing Analysis
• Synopsys Tools
• Programmable Logic
• Cadence Virtuoso
• Vlsi
• Application-Specific Integrated Circuits (Asic)
• Computer Architecture
• Verilog
• C++
• Chipscope
• Ncsim
• Sdram
• Vhdl
• Simulations
• Drc
• Dram
• Design Flow
• Physical Design
• Xilinx Ise
• Processors
• Soc
• Cadence Schematic Capture
• Fpga
• Embedded Software
• Asic
• Atpg
• Wifi
• Ieee 802.11
• Lvs