Mayur Mahajan

About Mayur Mahajan

13+ years of experience in physical design and implementation of complex SoCs, across Intel’s advanced process nodes, including 22nm, 14nm, 10nm, 7nm, Intel 4, and Intel 3.• Led full-chip integration and cluster-level floorplanning, successfully taping out multiple SoCs.• Expertise in all aspects of full-chip design planning, automated place-and-route (APR), and static timing analysis.• Delivered RFQs, assessed design practices for timing closure, and collaborated with external customers to implement best-known methods.• Proficient in Synopsys IC Compiler I & II (DP/APR), PrimeTime, Conformal, TCL, and Shell scripting.• Mentored interns and junior engineers on physical design flows, data collection, and scripting for timing and routing ECOs.

Experience

1. Staff Soc Design Engineer

   Intel

   Jun 2011 — Present · Portland, OR, US

   Led floorplan closure for E-core, delivering key layout collaterals to partition owners, and worked with the clock team to optimize mesh routing and timing-critical nets across partitions.• Achieved a 5% area improvement on E-core-based IP, utilizing Intel 4 and Intel 3 process nodes.• Developed a custom Full Chip Design Planning Flow to streamline partition floorplanning, pin placement, and collateral delivery across subsystems.• Engaged with external customers to develop and implement repeater flop insertion and routing optimization at the SoC level, improving performance and signal integrity.• Designed and maintained a custom Channel Partitions APR Flow, leading the execution of all channel blocks for efficient full-chip integration.• Collaborated directly with multiple foundry customers to meet power-performance-area (PPA) targets using synthesis and place-and-route (P&R) techniques.• Pioneered the Physical Guidance Flow for tighter correlation between DC and ICC compilers, improving runtime and achieving superior quality of results (QoR) and routability on 14nm.• Validated Arm Core 57 by optimizing floorplan, clock distribution, and routing, improving target frequency through enhanced track patterns and libraries.• Led full-chip cluster-level floorplanning, working closely with front-end teams to guide block and cluster architecture, enabling seamless physical design closure.• Developed and customized ICC-DP flow for abutted designs at 22nm, 14nm, and 10nm nodes, ensuring proper alignment of neighboring partitions and clean LVS handoff.• Led partition owners in debugging and root cause analysis to ensure high-quality execution of complex designs, incorporating multiple clock domains, voltages, and asynchronous paths.• Executed physical design from RTL to GDSII for high-frequency blocks in Micro Server Chips, utilizing SoC design flows (Design Compiler, ICC Compiler, PrimeTime).

Education

• California State University-Sacramento

  M.S.

  2007 — 2010

Skills

• Field-Programmable Gate Arrays (Fpga)
• Vlsi
• Logic Synthesis
• Rtl Design
• Soc
• Fpga
• Asic
• Static Timing Analysis
• Floorplanning
• Perl
• Eda
• Verilog
• Systemverilog
• System on a Chip (Soc)
• Tcl
• Physical Design