Mayur Gavali

About Mayur Gavali

8+ years of total experience in ASIC DFT which includes Spyglass, scan insertion, ATPG pattern generation & pattern simulations, timing constraints for DFT modes, ATE pattern delivery, debug & silicon bring up- I have been leading block level DFT activities for networking chips, data center chips & 3D technology chip- Starting from planning of DFT strategy, implementation, scheduling of IO’s, providing DFT configuration for proper scan insertion, proposing design fixes to designers to fix scan issues and achieve targeted test coverage, ATPG & simulations- Actively worked on flow automation for SDF simulations, exceptions processing & developing diagnostic flow to support diagnosis on ATE- Involved in full chip pattern porting, pattern demerging, and its simulations- Ownership of timing constraint generation for DFT modes and support to STA team- Involved in ATE pattern delivery, issue debug and silicon bring up- Experience with new fault models such as cell-aware & SDD- Simultaneously handled multiple critical project activities and delivered quality results- Worked on latest 5nm, 3nm, 2nm technology & 3D IC technology (5nm+3nm), participated in 7 tapeout- Experience of working with EDA vendors for tool updates, to get support required in tools and flow fixes- Trained & worked closely with new team members & intern to enable them for DFT execution.

Experience

1. Senior Staff Engineer

   Marvell Technology

   Apr 2026 — Present

Education

• Walchand college of engineering,sangli

  Bachelor of Technology (B.Tech.), Electronics

  2009 — 2013

• National Institute of electronics and IT

  Master of Technology (M.Tech.), Electronics Design Technology

  2014 — 2016

Skills

• Xilinx Ise
• Linux
• Fsm
• Verilog