Mayank Agrawal
Senior Engineer ASIC IP Design Verification at Micron Technology
- Role
- Senior Asic Ip Design Verification Engineer at Micron Technology
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Mayank Agrawal
Worked on RISC project and simulated on Verilog Vivado-Xilinx - Studied VLSI…
Experience
Senior Asic Ip Design Verification Engineer
May 2024 — Present · Hyderabad, IN
Education
Birla Institute of Technology and Science, Pilani
Master's degree
2019 — 2021
RSPS, Mathura
Inter School
2011 — 2013
Harcourt Butler Technological Institute(Now HBTU),Kanpur,India
B.Tech
2014 — 2018
PRFS, Mathura
High School
2007 — 2011
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