Maxwin Vallully
RTL Design Engineer at Qualcomm
- Role
- Senior Lead Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Maxwin Vallully
RTL Design Engineer with 5 years of experience specializing in the development and integration of complex digital IPs. Skilled in SystemVerilog and Verilog, with hands-on expertise using industry-standard tools including Spyglass Lint, CDC, Synopsys Verdi, JasperGold, and Conformal Low Power. Proven track record in leading and contributing to all phases of the RTL design cycle—architecture, micro-architecture, coding, verification planning, and both pre- and post-silicon debug. Experienced in collaborating with cross-functional and geographically distributed teams to deliver reliable design solutions. Holds a Master’s degree in Microelectronics from BITS Pilani and a Bachelor’s in Electronics and Telecommunication from University of Mumbai
Experience
Senior Lead Engineer
Dec 2024 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Master of Engineering - MEng, Microelectronics
2018 — 2020
SIES College of Arts and Science
HSC
2010 — 2012
University of Mumbai
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
2012 — 2016
St. Therese Convent High School
SSC
1998 — 2010
Skills
- Xilinx
- Microsoft Office
- Vlsi
- C
- Programming
- Matlab
- C++
- Mixed Signal
- Embedded Systems
- Microsoft Powerpoint
- Arduino
- Very-Large-Scale Integration (Vlsi)
- Microsoft Word
- Microsoft Excel
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