Maulin Sheth

About Maulin Sheth

Experience in Scan insertion using Synopsys DFT-Compiler and Formal Verification using Synopsys Formality.Experience in ATPG (Stuck-At and TDT) using Synopsys TetraMAX.Worked on Test Coverage improvement, Low Power ATPG.Experience on Scan and Functional IP test pattern with and w/o timing Validation using VCS and NC-Verilog.Good knowledge of Perl Scripting and Makefile based flow creation.Hands on debugging experience using DVE and Verdi.Knowledge on Advanced Fault Models like Path Delat, Bridging, SDDKnowledge of Scan Compression, JTAG, architecture.Skill Set :HDL : VerilogSynopsys Tools : DFT-Compiler, TetraMAX, Formality, VCS.Cadence : NC-Verilog, Sim-visionScripting : PerlGoals- Keep Learning. Strengthen Ability To View Future- To enhance and keep Working Environment Sound And Motivating- To be a significant contributor In the team.

Experience

1. Ic Design Engineer

   Broadcom

   Feb 2018 — Present · Bengaluru, IN

Education

• BIRLA VISHVAKARMA MAHA VIDHYALAYA(GIA), V.V.NAGAR

  B.E, Electronics and Telecommunication

  2006 — 2010

• Nirma Institute Of Technology

  Master of Technology (M.Tech.), VLSI

  2010 — 2012

Skills

• Perl
• Formal Verification
• Fpga
• Asic
• Very-Large-Scale Integration (Vlsi)
• Rtl Design
• Rtl Verification
• Verilog
• Xilinx
• Atpg
• Verification
• Digital Circuit Design
• System on a Chip (Soc)
• C++
• Cadence
• Debugging
• Application-Specific Integrated Circuits (Asic)
• Vhdl
• Synopsys Tools
• Testing
• Integrated Circuit Design
• Soc
• C
• Dft
• Vlsi
• Tlm
• Systemc
• Jtag