Matthew Grimm
- Role
- Asic Soc Design Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
Experience
Asic Soc Design Engineer
Jun 2018 — Present
ASIC Design Execution- Running Synthesis, Place and Route, and Timing- Timing Convergence.
Education
Portland State University
Master's degree, Electrical Engineering
2015 — 2017
Portland State University
Bachelor's degree, Electrical Engineering
2011 — 2013
Portland Community College
Associate's degree, Electrical and Electronics Engineering
2009 — 2011
Skills
- Vhdl
- Archives
- Agilent Ads
- Layout
- Functional Verification
- Electrical Engineering
- Microwave Engineering
- Soc
- Verilog
- Integrated Circuit Design
- Pvs
- Cadence Virtuoso
- Semiconductors
- Cad
- Analog Circuit Design
- Spice
- Hspice
- Static Timing Analysis
- System on a Chip (Soc)
- Cmos
- Microelectronics
- Drc
- Preventive Maintenance
- Eda
- Asic
- Ltspice
- Silicon Validation
- Unix
- Rf Engineering
- Rtl Design
- Vlsi
- Circuit Design
- Pcb Design
- Matlab
- Modelsim
- Pspice
- Fpga
- Customer Support
- Calibre
- C/C++ Programming
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