Matteo Vit

Director Principal Design Engineer @Starware Design Limited

Cambridge, GB

ASIC/FPGA design and verification (Xilinx and Altera; ISE/Vivado and Quartus; verification with UVVM, Cototb; QEMU-FPGA co-simulation, AI accelerators). Devops for FPGA.AI architecture design for RTL implementation.Hardware design (FPGAs, microprocessors/microcontrollers, digital video I/Os, mixed-signals (ADCs, DACs), switching DC/DCs, FMC boards, high speed (PCIe, DDRx)).Linux device drivers.Yocto customisation (new packages, patches, etc) and integration with CI.Zephyr.Test systems design and implementation (Python/RobotFramework, NI VISA instruments integration, PyQT GUI).Member of the IoT Security Foundation.

I.T.I. "A. Malignani" - Cervignano del Friuli (UD)

Electronics

Università degli Studi di Trieste

Master of Science (MSc)