Marwan Eid
Jr Layout Design Engineer @Si-Vision
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WORK HISTORY
Jr Layout Design Engineer @Si-Vision
Cairo, EG
Researching and developing UCIe PHY layout designs on advanced process nodes to enable high-performance interconnects- Implementing and verifying full-custom digital and analog layouts using Synopsys (Custom Compiler, ICV)- Performing physical verification, including DRC, LVS, ERC, PERC, ANT, and EM/IR analysis- Collaborating with digital and analog design teams to meet performance targets and ensure layout quality.
ABOUT MARWAN EID
Dedicated Nanotechnology and Nanoelectronics Engineering graduate with a solid academic background and hands-on experience in digital design and verification, VLSI, and computer architecture. Seeking an industry position to apply my expertise and skills, contributing to cutting-edge projects.
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