Maruthi Srinivas Narasimhan

About Maruthi Srinivas Narasimhan

Technical Fellow | Front-End Design & Verification Leader | Expert in Formal, Low Power & Sign-Off Methodologies:With 24+ years of hands-on experience in front-end SoC design and verification, I specialize in building scalable methodologies across formal/static verification, low power flows, assertion strategies, and sign-off closure. Currently, I serve as Technical Director at Krutrim SI Designs, leading verification methodology and architecture for India’s first AI server chip.Throughout my career, I’ve solved complex design challenges using formal techniques, driven coverage closure and sign-off at scale, and built verification ecosystems that deliver first-silicon success. At Samsung Semiconductor R&D, I led a 10-member formal team and 40+ extended engineers to raise silicon quality in NVMe projects. Prior to that, I drove global methodology at Qualcomm and championed formal adoption industry-wide at Cadence. Specialties:• Front-End RTL & DV Architecture• Formal Verification & Assertion-Based Methodology• Static Verification, Lint, CDC, Equivalence Check• UPF/CPF Low Power Verification• Formal Sign-off & Coverage Closure• Debug & resolution of complex design issues• Technical Mentorship & Cross-functional LeadershipI\'m an author of 30+ technical publications, a keynote speaker and panelist, and hold a patent (Ref: WI-20••••••81-US0). I’m passionate about applying deep technical skills to influence architecture, guide teams, and advance sign-off methodologies for next-gen compute platforms in AI, HPC, and data center domains.

Experience

1. Principal Engineer

   Arm

   Oct 2025 — Present

Education

• University of Madras

  BE, E.E.E

  1997 — 2000

• Vionix School of VLSI Design

  PG Diploma & internship, VLSI Design

• Manipal Academy of Higher Education (MS-VLSI)

  Master of Science (MS), VLSI CAD and Low power

  2007 — 2009

Skills

• Low-Power Design
• Upf
• Functional Verification
• Embedded Systems
• Eda
• Spice
• Field-Programmable Gate Arrays (Fpga)
• Mixed Signal
• Fpga
• Model Checking
• Asic
• Altera
• Logic Synthesis
• Vhdl
• Simulations
• Cmos
• Rtl Coding
• Jasper
• Systemverilog
• Emulation
• Product Lifecycle Management
• Vlsi
• Usb
• Programming Languages
• Formal Verification
• Dft
• Application-Specific Integrated Circuits (Asic)
• Rtos
• Verilog
• Algorithms
• Physical Design
• Python
• Eco
• Soc
• Sv
• Cpf