Marri Akhil

About Marri Akhil

Physical Design (Synthesis) Expert-> Experienced professional with Strong Expertise in Synthesis and Netlist generation for Next generation GPUs-> Specialized in performing block-level synthesis and improving PPA metrics using the Cadence-Genus synthesis tool-> Proficient in writing TCL scripts to create new flows and augment tool features- In-depth knowledge of ASIC/FPGA design flow from RTL design to GDSII, Performed DRC & LVS checks, Static Timing Analysis (STA)- Experienced in working with Industry tools such as Cadence Virtuoso and Encounter, Synopsis Design compiler, and Calibre DRC/LVS.Technical Skills:1. Cadence EDA Tools: Cerebrus Intelligent Chip Explorer, Genus Synthesis Solutions, Innovus Implementation System, Conformal Equivalence Checker.2. Synopsys EDA Tools: Fusion Compiler (Synthesis, CTS, Route), RTL-Architect, DSO.ai, Native Fusion.ai, Prime-power.2. Programming & Scripting Languages: System Verilog, Verilog HDL, TCL.

Experience

1. Physical Synthesis Cad Engineer

   Apple

   Apr 2026 — Present · Austin, TX, US

Education

• Vellore Institute of Technology

  Bachelor’s Degree, Electronics and Communications Engineering

  2012 — 2016

• Ira A. Fulton Schools of Engineering at Arizona State University

  Master of Science - MS, Computer Engineering (Electrical Engineering)

  2017 — 2019

• Narayana Junior College

  High School, M.P.C

  2010 — 2012

Skills

• Microsoft Office
• Verilog
• Vhdl
• Matlab
• C
• Teamwork
• Riverbed
• Ni Multisim
• Proteus
• Modelsim
• Altera Quartus
• Network Operations Center (Noc)
• Microsoft Word