Mark Keane
Ic Physical Design @Qualcomm
Glasgow, GB
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Sep 2015 — Present
Ic Physical Design @Qualcomm
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RTL to GDS2 Digital Physical Design & Analog/RF/PMU IC layout
EDUCATION
N/A
University of Paisley
Bsc Engineering
N/A
James Watt College
HNC Electrical & Electronic Engineering
SKILLS
Timing ClosureTapeoutVerilogCmosIntegrated Circuits (Ic)SocAsicMixed SignalRfApplication-Specific Integrated Circuits (Asic)Physical VerificationCadence VirtuosoSystem on a Chip (Soc)EdaPhysical DesignRtl DesignFloorplanningStatic Timing AnalysisIcSemiconductorsAnalog Circuit Design
ABOUT MARK KEANE
Analog IP toplevel layout, RF, PMU, mixed signal IC custom layout down to 6nm…
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