Mark Doczy

About Mark Doczy

Results-driven operations director with a proven record of transforming safety, quality, through put, and cost performance in a high-complexity 300mm semiconductor research and prototyping facility. Expert in managing large-scale capital projects to rapidly retool and reconfigure advanced research environments, ensuring sustained competitiveness and innovation readiness. Combines deep technical expertise as an engineer and physicist—holding over 200 U.S. patents—with sharp business acumen and data-driven decision-making. Skilled in leading cross-functional teams across operations, facilities, equipment engineering, and R&D. Recognized for critical thinking, problem-solving, and exceptional interpersonal communication. Trusted partner to executive leadership in driving strategy, operational excellence, and breakthrough technology developmentMy expertise includes Thin Films and Etch as applied to VLSI of CMOS, NAND, and STT-RAM technologies. With a Ph.D. in plasma physics from the University of Wisconsin, I have a strong foundation in fundamental physics of semiconductor processing and device physics. Additionally, I bring extensive experience in research lab management, operations, chemical safety, and equipment installation. I am skilled in leading cross-functional teams, leveraging exceptional critical thinking, problem-solving, and interpersonal skills to achieve breakthrough advancements and establish industry leadership.I was a recipient of 2012 SEMI Award for North America for pioneering work in the development, integration and introduction of a successful high-k dielectric and metal electrode gate state for 45nm CMOS IC production.

Experience

1. Semiconductor Research Engineering Manager

   Intel

   Sep 2017 — Present · Hillsboro, OR, US

   Direct a 70-person organization overseeing a sq. ft. advanced research facility, including sq. ft. of Class 1 cleanroom and sq. ft. of laboratory space, ensuring safe, high-quality, and efficient operations. • Optimized processing workflows in a 300mm semiconductor research fab, collaborating with a high-volume manufacturing site to achieve a 70% increase in wafer throughput. • Spearheaded cross-functional coordination among engineers, project managers, and trades to reduce construction cycle times by 50%, enabling the rapid installation of first-of-kind tools and retooling of over half the factory’s capacity within four years. • Led construction and capacity planning for Intel’s quantum computing research lab, aligning infra structure investments with cutting-edge technical requirements. • Reduced ergonomic-related injury rates by 10X over two years by implementing an ergonomic risk assessment program, reconfiguring workspaces, and deploying behavioral intervention tools such as break reminder software. • Championed inclusive career development initiatives by establishing advancement pathways for senior technicians to transition into engineering and project management roles, increasing internal mobility and technical leadership capacity

Education

• University of Illinois Urbana-Champaign

  Bachelor's degree

• University of Wisconsin-Madison

  Ph.D

Skills

• Characterization
• Device Characterization
• Photolithography
• Silicon
• Semiconductor Industry
• Chemical Vapor Deposition (Cvd)
• Spc
• Lithography
• Jmp
• Mems
• Integration
• Simulations
• Electronics
• Process Integration
• Ic
• Design of Experiments
• Semiconductors
• Semiconductor Device
• Physics
• Thin Films
• Cvd
• Cmos
• Integrated Circuits (Ic)