Mark Sternberg
VP, Engineering @高通
Toronto, ON, CA
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jan 2009 — Present
VP, Engineering @高通
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CA
Low power AI sub-system IP lead (2022 - Present)- Display Project Engineer: September (2011 – Present)- Overall Display IP lead - Team owns display architecture, algorithm development, performance/power modeling & tools- MSM8974 SoC architecture lead
EDUCATION
1993 — 1997
McGill University
B Eng, Electrical Engineering
SKILLS
SocVerilogAsicEdaRtl DesignTiming Closure
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