Mark Lyons
Layout Designer at pSemi, A Murata Company
- Role
- Layout Designer at pSemi, A Murata Company
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Mark Lyons
Senior Layout Designer with over 20 years of physical chip design experience.…
Experience
Layout Designer
Mar 2019 — Present · Austin, TX, US
Education
Austin Community College
Engineering Design Graphics, Electrical and Electronics Engineering
1986 — 1989
Skills
- Parasitic Extraction
- Microsoft Office
- Asic
- Calibre Physical Vericiation
- Soc
- Analog
- Semiconductors
- Chip Level and Block Level Integration
- Microprocessors
- Lvs
- Mentor Graphics Ic Studio
- Ic
- Drc/Lvs/Erc/Antenna
- Lef & Def
- Cadence Virtuoso Xl
- Perl
- Eda
- Drc
- Physical Design
- Signal Integrity Analysis and Repair
- Unix
- Nanoencounter
- Windows Office
- Vi
- Floorplanning
- Physical Verification
- Analog / Digital Layout Design
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