Mariya Davis
Technical Lead at HCL Tech
- Role
- Technical Lead at HCLTech
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Mariya Davis
Currently working on TSMC 4 nm SERDES design for CISCO.Good Knowledge in tools like cadence (Virtuoso), Calibre verification tool. Experienced in TSMC sub micron technology nodes.Currently working on TSMC 5 nm. Experienced in INTEL Genesys layout tool in 10nm, 10++ nm and using CPDS for verification.Hands on experience in using ADT in custom layout design.Designed layouts - floorplanning, placement, routingINTEGRATION, LVS, DRC, ERC Cleanup & ECO Changes.Have worked on GIO in SRAM Memory.Worked on memory leaf cells with different cell height, area constraint and with respect to top level architecture.Experienced in TSMC 3 nm,7nm, 6nm and 5nm nodes. Capable of performing custom layout for FinFet technologies.Good knowledge of memory cell architecture, chip fabrication, CMOS second order effects like Antenna effect, short channel effect, latchup, LOD, Electromigration, hot carrier effect.
Experience
Technical Lead
Apr 2023 — Present · Bengaluru, IN
Education
BITS Pilani Work Integrated Learning Programmes
Master of Technology - MTech
2019 — 2023
Mahatma Gandhi University
BSc Physics
2014 — 2017
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