Maria Anjali Kennedy Chettiar
CPU Core RTL Design Engineer
- Role
- Cpu Core Rtl Design Engineer at Intel
- Location
- Sacramento, CA, US
- LinkedIn followers
- 500 followers
About Maria Anjali Kennedy Chettiar
Our team at Intel harnesses my expertise in RTL design and electronics, where I contribute to the Out-of-Order cluster and the Reorder Buffer (ROB) unit, ensuring the microarchitecture we develop meets cutting-edge standards. With a strong foundation from the University of Southern California, my role involves collaborating across clusters and spearheading the validation process, which is pivotal to our product\'s success.Leveraging my academic background in VLSI Design, I\'ve played a key role in the successful tape-out of an ASIC, a milestone that underscores our commitment to innovation and excellence. My experience is complemented by a deep understanding of high-performance computer architecture, allowing us to push the boundaries of processor design and functionality.
Experience
Cpu Core Rtl Design Engineer
Jan 2020 — Present · Sacramento, CA, US
Working in the design of Intel Core Microarchitecture, specifically, in the Out-of-Order cluster and owning rtl design effort for Reorder Buffer (ROB) unit.My responsibilities include:• Reviewing Microarchitectural Spec for new features with Validators and involved in code reviews, test plan review and robust validation plans.• Cross cluster collaboration with designers for multi-cluster features.• Debugging SVA failures and Reference checker failures using Verdi waveform viewer and debug logs.• Verifying design by developing robust System Verilog Assertions (SVA). Own RTL design for a whole block in Intel core Processor and contributed towards successfully taping out an ASIC. Worked on designing performance features for my unit ( Reorder Buffer ) and drove Architectural features which will impact different teams. Focused on coding power optimization features for my unit. Worked extensively on clock gating and LCB CB optimization features.
Education
University of Mumbai
Bachelor of Engineering - BE, Electronics and Telecommunication Engineering
2013 — 2017
University of Southern California
Master of Science - MS, VLSI DESIGN
2018 — 2019
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