Marco Aiello
Principal Fpga Design and Verification Engineer @Indra Group UK & Ireland
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WORK HISTORY
Principal Fpga Design and Verification Engineer @Indra Group UK & Ireland
Market Deeping, GB
EDUCATION
Università degli Studi di Napoli Federico II
Electronic Engineering MS Degree, microelectronic, operating systems, embedded systems, VHDL, advanced computer science
ABOUT MARCO AIELLO
Senior FPGA design engineer, with more than 10 years of professional experience in the programmable logic field. In depth experience in the image acquisition and processing domain, in challenging environments, mainly in the defence sector. Proficient with Xilinx devices across several families, with in depth knowledge of the VHDL language. Capable of implementing hardware accelerators starting from a Matlab or C/C++ description by using HLS, Xilinx System Generator for DSP. Good knowledge of the Matlab tool, of Simulink and its toolboxes for automatic code generation, and fixed point design and analysis. Skilled in the whole Vivado workflow from the ground up, and with a solid understanding of embedded systems and HPC on Mpsoc platforms. Equipped with good low level C programming skills, and able to use Linux OS and RTOSes. Well acquainted in bridging the FPGA, algorithm hardware acceleration and embedded firmware world. At ease in helping in the development of the embedded software infrastructure. Well versed and eager to learn new skills, with little or no supervision at all. Author and coauthor of many publications on international magazines and conferences.
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