Marc Jansen

About Marc Jansen

Well-rounded Design for Test (DFT) Engineer with hands-on experience in all phases of the DFT life-cycle, from block-level RTL design, debug and verification to chip-level DFT architecture development and insertion, chip bring-up, and on-going manufacturing-test support- Experienced in all of facets of DFT design and verification, including JTAG, BSCAN, compressed-scan and MBIST- Very well-versed in Memory BIST design principles, from RTL design and verification to vector generation and failure-analysis of manufacturing defects- Comfortable making trade-offs between design requirements and their impacts on synthesis, timing, and physical placement.

Experience

1. Senior Principle Dft Engineer

   Ampere

   Mar 2025 — Present

Education

• Western Michigan University

  BSEE, Electrical Engineering

  1995 — 1997

Skills

• Tcl
• Static Timing Analysis
• Digital Electronics
• Timing Closure
• Debugging
• Rtl Design
• Linux
• Modelsim
• Perl
• Embedded Systems
• Eda
• Pcb Design
• Hardware Architecture
• Soc
• Verilog
• Integrated Circuit Design
• Microprocessors
• Electronics
• Semiconductors
• Jtag
• Fpga
• Embedded Software
• Asic
• Dft
• Testing
• Electrical Engineering
• Ic
• Vlsi
• Unix
• Vhdl
• Simulations