Maram Siri Reddy
Rtl Design and Verification Engineer Trainee @Vlsi First
Hyderabad, TG, IN
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WORK HISTORY
Sep 2024 — Present
Rtl Design and Verification Engineer Trainee @Vlsi First
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Hyderabad, IN
ABOUT MARAM SIRI REDDY
Language: C Programming,Verilog,System Verilog,python. Methodology: UVM Protocols:…
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