Manu Yeeshu
Verification engineer
- Role
- Pre Silicon Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Pre Silicon Verification Engineer
May 2022 — Present · Bengaluru, IN
Education
A.M.U City High School
High School
1996 — 2001
PESIT
B.E., Electronics and Communications Engineering
2003 — 2007
Senior secondary school aligarh
12th, Engineering
2001 — 2003
Skills
- Assertions Based Verification Through Psl
- Cortex R4
- Rtl and Gls Simulations
- Ncsim
- Debugging
- Rtl Coding
- C
- Post Silicon Debug
- Asic
- Ahb
- Amba Ahb
- Verilog
- Modelsim
- Static Timing Analysis
- System Verilog Assertions
- Ftdl
- Assembly Language
- Systemverilog
- Vhdl
- Simulations
- Soc Verification Using Arm Asembly Language
- Vlsi
- Functional Verification
- Formal Verification
- Soc
- Arm
- Axi
- Rtl Design
- Embedded Systems
- Eda
- Tcl
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