Mansi Jotwani
Design Verification Engineering Manager at Intel Corporation
- Role
- Design Verification Engineering Manager at Intel
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineering Manager
Jul 2018 — Present
Skills
- Verilog
- Debugging
- Perl
- Asic
- C
- Vlsi
- Testing
- Hardware
- Soc
- Fpga
- Functional Verification
- Unix
- Embedded Systems
- Linux
- Computer Architecture
- Application-Specific Integrated Circuits (Asic)
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