Manoz Palaparthi

About Manoz Palaparthi

With over nine years of experience in product management for the semiconductor industry, I am a senior staff product manager at Synopsys, the global leader in electronic design automation. I lead the product strategy, roadmap, and execution for Static Timing Analsyis solutions, enabling our customers to signoff closure goals for their advanced ASIC products. I have extensive expertise in low power design, PrimeTime, and physical verification, as well as skills in power analysis and signoff, and rail analysis and power integrity. I have successfully launched multiple new products working closely with engineering, sales, and support teams, as well as with key customers and partners. I am passionate about creating innovative and customer-centric products that solve complex design challenges and deliver value to the market.

Experience

1. Director of Product Management

   Synopsys Inc

   Dec 2022 — Present · Sunnyvale, CA, US

   Stating Timing AnalysisAI for Chip DesignNew Product Strategy from Ideation to Go To MarketStrategy, Product Management for product lines

Education

• Birla Institute of Technology and Science, Pilani

  Bachelor of Engineering - BE

Skills

• Parasitic Extraction
• Electrical Engineering
• Timing
• Verilog
• Logic Synthesis
• Formal Verification
• Clock Tree Synthesis
• Debugging
• Asic
• Dft
• Design Methodology
• Power Management
• Soc
• C++
• Logic Design
• Power Planning
• Tcl
• Semiconductors
• Digital Design
• Hardware Design
• Microprocessors
• Ic
• Power Estimation
• Primetime
• Perl
• Route
• Eda
• Cmos
• Drc
• Algorithms
• Physical Design
• C
• Low-Power Design
• Arm
• Electronics
• Semiconductor Design
• Low Power Design
• Timing Closure
• Signal Integrity
• Simulation