Manoj Murali
- Role
- Soc Physical Design Timing Engineer at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Manoj Murali
I am a passionate and experienced Static Timing Analysis(STA) Engineer with 12+ years of…
Experience
Soc Physical Design Timing Engineer
Mar 2020 — Present
Skills
- Power Analysis
- Equivalence Checking
- Tcl
- Digital Electronics
- Verilog
- C
- Very-Large-Scale Integration (Vlsi)
- Physical Design
- Static Timing Analysis
- Logic Synthesis
- Vhdl
- Vlsi
- Systemverilog
- Eda
- Timing Closure
- Soc
- Application-Specific Integrated Circuits (Asic)
- Asic
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