Manoj Rote

Lead Design Engineer at CDNS

Role
Lead Design Engineer at Cadence
Location
Pune District, MH, IN
LinkedIn followers
500 followers

Experience

  1. Lead Design Engineer

    Cadence

    Jan 2021 — Present · Pune, IN

Skills

  • C
  • Xilinx Ise
  • Matlab
  • Vlsi
  • Verilog
  • Gate Level Simulation
  • Fpga
  • Functional Verification
  • Digital Image Processing
  • Vhdl
  • Algorithms
  • Signal Processing
  • Microcontrollers
  • Modelsim
  • Application-Specific Integrated Circuits (Asic)
  • Electronics
  • Vivado Hls
  • Digital Electronics

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Manoj Rote — Lead Design Engineer at Cadence in Pune District, MH, IN | Unifers