Manoj Kumar Pedireddi
Senior Silicon Design Engineer
- Role
- Sr Silicon Design Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Manoj Kumar Pedireddi
Verification engineer with a demonstrated history of working in the VLSI industry. Having 5+ years of experience in Design Verification and have been involved in IP,SOC and ASIC projects. Skilled in Universal Verification Methodology (UVM), System Verilog, Verilog. Strong engineering professional with a B. Tech focused in Electronics and Communication Engineering.
Experience
Sr Silicon Design Engineer
Oct 2021 — Present · Bengaluru, IN
Education
Centre for Development of Advanced Computing (C-DAC)
PG-Diploma, VLSI Design
2015 — 2016
CHAITANYA ENGINEERING COLLEGE
Bachelor of Technology (B.Tech.), Electronics and communication engineering
2011 — 2015
Skills
- Windows
- Powerpoint
- Microsoft Excel
- Leadership
- Teamwork
- Microsoft Office
- Vlsi
- Microsoft Word
- Electronics
- Public Speaking
- Engineering
- Fpga
- C
- Programming
- Asic
- System Verilog
- Xilinx Ise
- Matlab
- Very-Large-Scale Integration (Vlsi)
- Vhdl
- Management
- Perl
- Linux
- Modelsim
- Verilog
- Digital Circuit Design
- C++
- Universal Verification Methodology (Uvm)
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