Manoj Autade
Principal Design Engineer at Cadence Design Systems
- Role
- Principal Design Engineer at Cadence
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
About Manoj Autade
Working as Principal Design Verification engineer in Cadence (TIP).Skill set: UVM, System Verilog, SVA, perl, Assembly language, IPXACT and palladium based emulation platform (ICE).Currently leading the verification of complete Debug module of all the Xtensa products and developing/maintaining palladium (ICE) TB for cadence deep neural network accelerator (DNA).Xtensa debug module consists of On Chip Debug (OCD), TRAX (Compressed program trace), Integrated Logic Analyser (ILA), Performance Counters, JTAG, APB and TAP state machine.Also, responsible for all Reset drivers and Stable generation logic of all the Xtensa version.Responsible for verification of complete DNA product (customer package), it involves co-coordinating with all the teams viz. RTL, unit level DV, Software team (XNNC), xtsc (system C model) team and back end team. Keeping all these teams in sync and verify the final product and give performance numbers for AI networks.
Experience
Principal Design Engineer
Jul 2021 — Present · Pune, IN
Leading verification of Interrupt Controller, OCD, TRAX, Debug, Reset, ILA, Traceport for all the Xtensa product lines
Education
Sinhgad College of Engineering
Bachelor's degree
2008 — 2012
IITB, Mumbai
Master's degree
2013 — 2015
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