Manjusha Bhattacharyya

About Manjusha Bhattacharyya

M.Tech in VLSI DESIGN. • Thorough understanding of the concepts of Digital logic Design, RTL2GDSII Flow, STA. • Understood the concept behind timing report analysis, Synthesis, APR, CTS along with an expertise in the tools. • Exposure to various STA concepts like: OCV, AOCV, CRPR, Time borrowing, Effect of clock skew on timing. • Performed Static Timing Analysis of various paths (REGIN, REGOUT, Multi-cycle, Half-cycle) in MCMM mode. • Performed analysis of log files at various stage of a design to understand the Sanity checks, Placement Optimization, CTS. • Worked on a project in 40nm technology to implement a block level Physical design to meet required IR drop, congestion free placement, CTS for targeted skew.

Experience

1. Senior Silicon Design Engineer

   AMD

   Jun 2025 — Present

Education

• Dibrugarh University

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

• Indira Gandhi Delhi Technical University for Women

  Master of Technology - MTech, VLSI

  2017 — 2019

• RV-VLSI

  Advanced Diploma in ASIC Design, Physical Design

  2020 — 2021

• Ramanujan junior college

  Higher Secondary, Science