Manjunath S
physical design engineer,Internship at Maven silicon,, experienced with synopsys tools like Fusion compiler, ICC2 compiler, DC compiler|Siemens tool like calibre| Synthesis | PNR Flow| Verification.
- Role
- Intern at Maven Silicon
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Manjunath S
As a dedicated Physical Design Engineer specializing in VLSI (Very Large Scale Integration), I bring a strong technical background in the semiconductor industry. With expertise in floorplanning, placement, routing, clock tree synthesis, timing closure, and power optimization, I contribute to the efficient design of high-performance, low-power integrated circuits. My experience spans from initial design conception through to tapeout, ensuring that complex SoC designs meet stringent performance, area, and power constraints. I am passionate about pushing the boundaries of chip design, utilizing state-of-the-art tools and methodologies such as Cadence, Synopsys, and Mentor Graphics. With a solid understanding of DRC, LVS, and IR drop analysis, I thrive in collaborative environments, working closely with cross-functional teams to drive innovation and deliver cutting-edge solutions in the semiconductor industry. Feel free to connect if you\'d like to discuss semiconductor technologies, industry trends, or opportunities in VLSI design!
Experience
Intern
Jul 2024 — Present · Bengaluru, IN
Education
Webster High School
SSLC
2017 — 2018
MEI Polytechnic
Diploma
2018 — 2021
RNS Institute of Technology - India
Bachelor of Engineering - BE
2022 — 2024
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