Manjunath N P

About Manjunath N P

9+ years of industry experience in ASIC Design with expertise in Physical Design, Power Integrity and Static Timing Analysis of Hard Macros and SoC.I drive innovation and efficiency in every project, and I prioritize measurable impact, quality, and continuous improvement.

Experience

1. Staff Design Engineer

   Qualcomm

   Nov 2025 — Present · Bengaluru, IN

   Physical Design of ASICs

Education

• Visvesvaraya Technological University

  Bachelor of Engineering (B.E.), Electronics and communication

  2012 — 2016

Skills

• Electronics
• Vlsi
• Digital Electronics
• Semiconductors
• Cmos
• Asic
• Physical Design
• Static Timing Analysis
• Logic Synthesis
• Linux
• C
• C++
• Verilog
• Analog Circuit Design
• System on a Chip (Soc)
• Eda
• Synopsys Ic Compiler
• Synopsys Design Compiler
• Synopsys Primetime
• Mentor Questasim
• Mentor Calibre
• Mentor Pyxis
• Shell Scripting
• Perl
• Tcl
• Rtl Design
• Rtl Verification
• Floorplanning
• Power Planning
• Ir Drop Analysis
• Std Cells Placement
• Clock Tree Synthesis
• Routing
• Design Rule Checking (Drc)
• Layout Versus Schematic (Lvs)
• Dfm
• Application-Specific Integrated Circuits (Asic)