Unifers.ai

Manish Tasodia

Design Verification Engineer at Excel vlsi Technologies / Verilog / System Verilog / UVM/Specman

Role
Design Verification Engineer at Excel VLSI Technologies
Location
Bhopal, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

Experience

  1. Design Verification Engineer

    Excel VLSI Technologies

    Mar 2022 — Present · Bengaluru, IN

Education

  • UIT RGPV

    Bachelor of Engineering - BE

  • RKDF UNIVERSITY

    POST GRADUATE

Find verified contacts for anyone on LinkedIn

Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.

Start for freeSee how it works

Free plan included · No credit card required

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.