Manish Desai

About Manish Desai

13+ years of ASIC design and verification experience including architecture development for design, HDL coding, Design Linting, Synthesis, STA, FullChip Verification.Worked on multiple IP\'s RTL development with all Quality tools, including USB3.1, USB4, PCIe, USB2HUB, other proprietary spec IPs.Worked on multiple proprietary logic architecting and IP developments, FPGA validations and debugging.

Experience

1. Senior Staff Engineer

   Qualcomm

   Nov 2024 — Present · Bengaluru, IN

Education

• Dharmsinh Desai University

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2007 — 2011

Skills

• Modelsim
• Logic Design
• I2c
• Usb3.1
• Gate Level Simulation
• Very-Large-Scale Integration (Vlsi)
• Functional Verification
• 1g/10g Ethernet
• Fpga
• Open Verification Methodology
• Asic
• Full Chip Simulation
• Logic Synthesis
• Lint
• Spi
• Amba Axi
• Amba Ahb
• Pcie
• Rtl Design
• Verification
• Systemverilog
• Jtag
• Pci Express
• Uart
• Scripting
• Application-Specific Integrated Circuits (Asic)
• Amba Apb
• Verilog
• Usb3.0
• Vlsi