Manish Choudhary

About Manish Choudhary

Hello! I, with a passion for technology and innovation in semiconductor, am an SRAM Design Engineer with 1.5+ year of hands-on experience in schematic-level memory design, simulation, and characterization. I specialize in 6T SRAM bitcell design, Static Noise Margin (SNM) analysis, and power-delay evaluation using Cadence Virtuoso and Spectre simulator.In addition to bitcell-level analysis, I have designed and verified a complete 8 bit memory IP including peripheral circuitry such as address decoders, sense amplifiers, write drivers, and control logic. My work involves corner-based margining using the SAED 32nm PDK, with a focus on transistor-level accuracy and circuit robustness. I enjoy solving design challenges in memory IP and optimizing circuit behaviour across PVT variations.Vision for the Future: I am passionate about VLSI and eager to contribute my skills to create robust integrated circuits. With my honesty and passion I want to build the technology that is changing the world and contribute something to the company’s growth.Looking forward to contributing to advanced CMOS memory design teams and cutting-edge VLSI development.

Experience

1. Trainee Engineer

   Exiger Technologies

   Feb 2024 — Present · Bengaluru, IN

   SRAM Design EngineerDesigned and simulated 6T SRAM bitcells at schematic levelPerformed SNM margin analysis using butterfly curvesCharacterized delay and power metrics across PVT cornersUsed Cadence Spectre simulator with SAED 32nm PDKDocumented simulation results with annotated waveforms and detailed reports

Education

• Jharkhand University of Technology (JUT), Ranchi

  Bachelor of Technology - BTech, Electrical and Electronics Engineering

• Government Polytechnic Kharsawan

  Diploma of Education, Electrical Engineering

• Atomic Energy Central School, Jadugora

  High School(12th), Computer Science