Mani Ramkumar

About Mani Ramkumar

Experienced SOC Physical Design Engineer & Leader with track record of successful tape outs on cutting edge nodes spanning diverse market segments such as Storage, Ultra Mobility SoCs, Network and Microservers. Proven track record of planning and executing SOCs with ability to scale to project needs. Building successful and passionate teams with focus to continuous improvement in implementation methods while fostering a highly collaborative environment to achieve best in class PPA.

Experience

1. Physical Design Lead

   Google

   Sep 2023 — Present · Austin, TX, US

Education

• University of Madras

  BE, Electrical & Electronics

  1996 — 2000

• Arizona State University

  Master Of Science, Electrical

  2001 — 2003

Skills

• Physical Verification
• Low-Power Design
• Timing Closure
• Formal Verification
• Vlsi
• Systemverilog
• Physical Design Rtl->Gds
• Very-Large-Scale Integration (Vlsi)
• System on a Chip (Soc)
• Physical Design
• Verilog
• Primetime
• Eda
• Asic
• Bist
• Rtl Design
• Ic
• Debugging
• Static Timing Analysis
• Synopsys Tools
• Dft
• Soc
• Timing
• Semiconductors