Manik Jindal

About Manik Jindal

I am an analytical and results-driven SoC Design-for-Test (DFT) Engineer with 9+ years of experience across Google, Intel, and Samsung R&D. My expertise lies in architecting and implementing robust DFT methodologies that ensure first-time-right silicon, high test coverage, and seamless post-silicon bring-up.I specialize in: • Scan Synthesis ensuring 100% scan insertion without DRC violations • ATPG & MBIST – Insertion, pattern generation, debug, and coverage closure • Pattern timing simulations & post-silicon bring-up for reliable production readiness • Automation (Perl, Python) – streamlining flows, reducing turnaround time, and improving efficiencyThroughout my career, I have collaborated with cross-functional teams to deliver high-quality SoCs on aggressive schedules. Alongside technical expertise, I actively mentor junior engineers and drive process improvements to scale organizational impact. Recognition • Foundry President’s Award – Samsung R&D (Apr 2018) • Spot Award – Samsung R&D (Oct 2017) • Employee of the Month – Samsung R&D (Jan 2017)I am passionate about bridging traditional DFT with emerging AI-driven automation and test solutions, ensuring scalability and innovation in next-generation semiconductor designs.

Experience

1. Soc Dft Engineer

   Google

   Aug 2023 — Present · Bengaluru, IN

   SoC DFT Engineer at Google Cloud, leading SCAN/ATPG strategy for complex SoCs. Driving coverage closure, enabling 100% scan insertion with zero DRCs, and mentoring junior engineers while collaborating with cross-functional teams to deliver robust testability.

Education

• Sri Guru Harkrishan Model School, Chandigarh

  Senior Secondary School, Sciences

  2008 — 2010

• Chandigarh College of Engineering & Technology (Degree Wing), Panjab University

  Bachelor’s Degree, Electronics and Communication Engineering

  2010 — 2014

• D.A.V. Public School, Chandigarh

  High School

  1998 — 2008

• International Institute of Information Technology Bangalore

  Master's Degree, Electronic System Design

  2014 — 2016

• Symbiosis Centre for Distance Learning

  Post Graduate Diploma in Business Administration, Management and Operations

  2018 — 2020

Skills

• Mentor Questasim
• Microsoft Office
• Xilinx Ise
• Electric Design Tool
• Synopsys Custom Designer
• Team Management
• Analog Circuit Design
• Red Hat Linux
• Python
• Cadence Schematic Capture
• Vlsi Circuit Design
• C
• Static Timing Analysis
• Cadence Virtuoso Layout Editor
• Perl Scripting
• C++
• Microcontrollers
• Verilog
• Mixed-Signal Ic Design
• Ltspice
• Cadence Encounter
• Cadence Spectre
• Eda