Manikanta Satyavarapu
Lead Design Verification Engineer @Cadence| EX-AMD | UALINK Protocol Phy Verification
- Role
- Lead Design Verification Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Experience
Lead Design Verification Engineer
Aug 2025 — Present · Bengaluru, IN
Working on UALINK phy vip development from scratch using Ethernet phy protocol- Owned and executed verification plan, driving implementation of- Serial agents (driver, monitor)- Common infrastructure (scoreboard)- Identifying and developing innovative test scenarios for robust coverage and functionality of UALINK phy interface
Education
Sasi Jr. College,Velivennu
Intermediate, M.P.C
2013 — 2015
Anil Neerukonda Institute Of Technology & Sciences
B.tech, Electrical, Electronics and Communications Engineering
2015 — 2019
Government High school, BAYYANGAUDEM
SSC, -
2008 — 2013
RV-VLSI DESIGN CENTRE
Advanced Diploma in RTL Design And Verification, vlsi
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