Manikanta Chitta
Physical Design Engineer @MosChip®
Signup · Get unlimited contacts
WORK HISTORY
Physical Design Engineer @MosChip®
Hyderabad, IN
Hyderabad, Telangana, India
EDUCATION
Sri Sunflower College of Engineering & Technology, Lankapalli (Challapalli), Ghantasala Mandal, -521131(CC-R8)
Bachelor of Technology
ABOUT MANIKANTA CHITTA
Through knowledge of concepts from RTL to GDS II and Static Timing analysis.Comprehensive understanding of Floor planning, Place & Route, timing closure, signal integrity closure, Physical verification, deep-submicron issues.Hand on experience in 7nm. Worked on AMD and Intel client Involved in Floor planning, Placement and routing, Timing closure, signoff extraction timing and ECO of 2Milion gate design in 7nm.Responsible to clean the Design and References flow with respect to Timing violation, DRC/ERC/ANTENNA/LVS/DFM Violations.Involved in standard Cell layout creation as per given specification and doing all checks(DRC/LVS).
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.