Manideep Maduri
Undergrad | Design Verification Engineer | RTL | SystemVerilog | UVM
- Role
- Design Verification Engineer at HCLTech
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Manideep Maduri
Hello and warm greetings!I am a recent graduate in Electronics and Communication Engineering from Geethanjali College of Engineering and Technology, with a strong passion for VLSI Design Verification. I have a solid foundation in Python and am currently undergoing intensive training at Maven Silicon, where I am honing my skills in design, Verilog, SystemVerilog, SVA, UVM, and functional coverage.Through this training, I have been actively working on various projects, applying industry-standard methodologies to ensure efficient and robust verification. I am eager to contribute my skills to the semiconductor industry and collaborate with professionals to enhance my expertise.Let\'s connect and discuss opportunities in the VLSI domain
Experience
Design Verification Engineer
Jul 2025 — Present · Bengaluru, IN
Education
Geethanjali College of Engineering and Technology
Bachelor of Technology - BTech
2020 — 2024
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