Mani Miriyala
ECE undergrad (ACET\'26) with 1.5+ yrs in VLSI front-end. Proficient in Verilog, System Verilog, RTL design, digital verification, UART, I2C, APB. Trained on Cadence Xcelium |VLSI Trainee @Technical Hub | IEEE Mem
- Role
- Technical Hub
- Location
- Kakinada Rural, AP, IN
- LinkedIn followers
- 500 followers
About Mani Miriyala
I\'m a Self Crtitic. I feel restless until my work is done.
Experience
Present
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